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CIRCUIT TECHNOLOGY
APPLICATION NOTE #108
CT2577 / 79 SmaRT Series Users Guide
Point of Contact: John Vanchieri Tel: (516) 752-2484
APPLICATION NOTE #108
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Table of Contents
Contents
MIL-STD-1553 Bus Interface Signals Hard Wired Interface Signals MIL-STD-1760 Signals Bus Interface Signals RT Status Word Discrete Inputs RT Discrete Signals BC Discrete Signals
Page
Signal Descriptions...............................................................................................................................................3-7
Remote Terminal (RT) Mode.............................................................................................................................8-21
Sequence of Operation Receive Command Message Illegalization MIL-STD-1760 Features 1760 Header Word Signals that Indicate Checksum Failure Block Transfer Logic READ (Receive) DMA Transfer Times Transmit Command MIL-STD-1760 Features Signals that Indicate Checksum Failure Block Transfer Logic / DMA Transfer Times WRITE Changing the Status Word Bits Device Status Bit Register Data Storage and Retrieval in Ram Sample Software Code Retriving or Loading Data to Ram Self Test Basic Operation Detailed Operation Summary of Operation
CT2577/79 RT/BT Memory Map Breakdown .................................................................................................. 22 RT/BT Device Memory Map Code Breakdown Description.....................................................................23-29
RT Status Word Control Sets BC Control Area RT/RX BC/TX Mode Area 00 - SA 00 (0) and BC Control 30 RT Receive / BC Transmit Subaddresses - SA 01-1E (1-30) RT/RX BC/TX Mode Area - SA 1F (31) RT/BC Control Area RT/BC Block Transfer Logic (BTL) Control and Self Test Control RT/TX BC/RX Mode Area - SA 00 (0) 30 RT Transmit / BC Receive Subaddresses -SA 01-1E (1-30) RT/TX BC/RX Mode Area - SA 1F (31) Broadcast RT/RX BC/TX Mode Area - SA 00 (0) 30 Broadcast RT Receive / BC Transmit Subaddresses - SA 01-1E (1-30) Broadcast RT/RX BC/TX Mode Area 1F - SA 1F (31)
CT2577/79 Part Ordering Information .........................................................................................................30-34
CT2577 - MIL-STD-1553 / 1760 Bus Controller / Remote Terminal CT2579 - McAir Bus Controller / Remote Terminal
CT2577/79 Pinouts...........................................................................................................................................35-41
CT2577-01-xx-F84 - 84 pin Quad Flatpack CT2577-11-xx-F84 - 84 pin Quad Flatpack CT2579-01-xx-F84 - 84 pin Quad Flatpack CT2579-11-xx-F84 - 84 pin Quad Flatpack CT2577-10-xx-P119 - 110 Pin Grid Array CT2579-10-xx-P119 - 110 Pin Grid Array
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Signal Descriptions
MIL-STD-1553 Bus Interface Signals
Data0(Bus) Connect to positive side of the external databus transformer for Bus 0 Ndata0(Bus) Connect to negative side of the external databus transformer for Bus 0 Data1(Bus) Connect to positive side of the external databus transformer for Bus 1 Ndata1(Bus) Connect to negative side of the external databus transformer for Bus 1
Hard Wired Interface Signals
AddrA-E Remote Terminal address inputs for the unit. ADDR A is the least significant bit and ADDR E is the most significant bit. RT Address inputs for the unit. AddrA is the LSB, AddrE is the MSB. Parity Bit for the RT Address inputs. AddrP must be set to ODD parity This signal sets the unit to respond with a status word within 4 uS (dead bus time) while in Remote Terminal mode. Subaddress 1F is also enabled to be a valid subaddress for data. Normally subaddress 00 and 1F are reserved for mode codes. "1" = 4 uS dead bus response time, subaddress 1F used for data. "0" = 12 uS response time, subaddress 1F used for mode codes. Select 8 or 16 bit subsystem data interface. In 8 bit mode only the lower 8 bits of the databus (DATA 0-7) are used for all data transfers. If left open circuit the device will default to 16 bit mode. "0" = 16 Bit Mode "1" = 8 Bit Mode Select VME or MULTIBUS subsystem interface. If left open circuit the device will default to VME mode. "0" = Multibus Mode "1" = VME Mode Select Remote Terminal wrap around to subaddress 1E. For this test to work correctly theunit must be in RT mode. The Bus Controller sends data to subaddress 1E which remains in the data buffer memory and is available to be sent back on the very next command by the Bus Controller. The data in the data buffer memory in this mode does not get transferred to the main RAM. If the very next command is not a transmit command to subaddress 1E, the data buffer memory is flushed and will respond normally to the next set of commands. If the wrap around test is enabled, data to subaddress 1E must be transferred in the correct sequence. "0" = Normal Mode "1" = Wrap Around Mode
AddrP MACAIR
NBIT16
VME
*WRAPEN
MIL-STD-1760 Signals
NENCHK Enables / Disables the internal hardware checksum generation and validation for both Remote Terminal and Bus Controller. When enabled, the circuitry will check all
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incoming data for correct checksum and generate the correct checksum word for an outgoing data transfer. "0" input to this pin ENABLES the checksum circuitry. "1" input to this pin Disables the checksum circuitry. NVALCHK Latched version of the STATUS signal. NVALCHK is latched on the falling edge of NCMDSTRB (RT) or NSTSTRB (BC) and will remain stable until the next NCMDSTRB or NSTSTRB. "0" output to this pin means the checksum was VALID. "1" output to this pin means the checksum was NOT VALID. Open drain output will toggle high or low on each incoming data word from the 1553 databus provided NENCHK is enabled. When the last data word is received the STATUS line is sampled by the protocol circuitry to determine if the checksum for the message is valid. At the end of the message, if STATUS is low then the checksum is not valid. This STATUS signal can be wired to several different pins to customise the units response to achecksum failure. STATUS can be wired to signals such as NILLCMD and NSR which would cause the message to be illegalised and set Service Request bit in the Status. In MIL-STD-1760, the first data word of a message is defined as a Header word. The NHDR signal indicates the presence of the Header word on the T0-T15 highway as it is received. The user can also read the Header word from RAM. "0" on this pin means the Header Word is on the T0-15 Bus When the store is released from the aircraft all the Remote Terminal address inputs go high causing signal STREL to go high Enables the Latched Address Option. Normally, the RT address lines are constantly monitored and compared to the incoming Command Word. When enabled, the RT address lines levels are internally latched every time the unit is reset. The latched RT address information is then compared to the incoming Command Word. This latched address function complies with the requirements of MIL-STD-1760. "0" on this pin means the RT address lines are NOT latched "1" on this pin means the RT address lines are latched
STATUS
NHDR
STREL LA
Bus Interface Signals
ADIN0-11 12 bit address input to the unit specifying what location the user will be accessing in the RAM / registers. These address inputs are inverted when the Multibus interface is selected. Indicates what mode the unit is in. "0" = RT Mode "1" = BC Mode Used as a Device Select. Signal to indicate the processor is addressing this unit. The user can use this signal tied to an address decoder to enable the unit for a read/write operation. "0" = Enable unit for I/O operations "1" = DISABLE unit for I/O operations 16 Mhz clock system clock.
4
BCNRT
NCARDEN
C16Mhz
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DATA0-15
16 bit bidirectional data highway access to internal RAM and registers. When in 8 bit mode only DATA 0-7 are used. Data inputs / outputs are inverted when the Multibus interface is selected. After a write / read cycle has begun, this signal indicates that the write / read operation to the unit has been acknowledged and that access has been granted. Read data is available and write data is complete. The user can complete the write / read cycle. "0" = Cycle is acknowledged, access granted. "1" = No acknowledge, wait. Empty flag for the Command / Status FIFO memory which can store up to 32 command words (RT) or 32 status words (BC). In RT mode the memory will store all command words that have accessed the main RAM. This includes all standard commands to receive and transmit data from the main RAM and mode codes with data that require subsystem involvement ie. Synchronize With Data and Transmit Vector Word. In BC mode all status responses are stored in this memory. Access to this memory is gained by reading from address 0 00 00. "0" output to this pin means the FIFO is empty (no words). "1" output to this pin means the FIFO is NOT empty (has words to be read). Full flag for the Command / Status FIFO memory. When the signal goes low the memoryis full and will not store any more data. Bidirectional reset pin. Interface to this pin should be in the form of an open collector pull down driver. The unit will be reset when a low level input is asserted on power up. The pin is bidirectional in that the unit will drive the signal out low after the status response of the mode code Reset Remote Terminal. Upon reset the unit will initialise to RT mode and will be able to respond immediately after the rising edge of NRES. 16 bit bidirectional data highway access to internal RAM and registers. When in 8 bit mode only DATA 0-7 are used. Data inputs / outputs are inverted when the Multibus interface is selected. Allows the user to have access to the MIL-STD-1553 bus traffic in real time. The user can utilize this bus for message illegalization and read words such as Synch w/Data directly off the T0-15 bus. Utilizing NDATA signal, the user can read the data words off the T0-15 bus as the DMA burst is transferring the data into RAM. Upper byte: When the unit is in 8 bit mode this signal is used as the LSB of the address lines. In 16 bit mode the signal is not used and the LSB of the address lines is ADIN 0. VME Mode Data Strobe for a data transfer 0 = Read/Write data 1 = Tri-state the Data 0-15 bus
NACK
NEMPTY
NFULL NRES
T0-15
UB
NRD
Multibus Mode:Read strobe for a data transfer 0 = Read data FROM the unit TO the Subsystem 1 = Tri-state the Data0-15 bus NWR VME Mode Read/Write direction flag for a NRD data strobe 0 = Write data FROM Subsystem TO the Device 1 = Read data FROM Device unit TO the Subsystem
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Multibus Mode:Write strobe for a data transfer 0 = Write data FROM the Subsystem TO the Device 1 = Tri-state the Data0-15 bus
RT Status Word Discrete Inputs
The following signals are inputs to set the appropriate bits in the RT Status word. All inputs are sampled after the NVCR signal. These RT Status Word inputs should be latched by NVCR and remain stable until the next NVCR signal. All the inputs listed below are active low. To set any of the appropriate bits, the user must pull that input "low" ("0") NME Message Error, illegalizes message. Command will not be stored in Command / Status memory and no transfers to / from main RAM will take place. No data will be transmitted following the status. Sets the Terminal Flag bit Sets the Service Request bit Sets the Subsystem Busy bit Sets the Subsystem Flag bit Sets the Dynamic Bus Control Accept bit in response to the Mode Code "Dynamic Bus Control Request"
NTF NSR NBUSY NSSFLAG NDBCA
RT Discrete Signals
BCST Output high indicates command received was a broadcast. Signal will remain high until next command is received.
"1" = Broadcast Command was received
MCDET Output high indicates command received was a mode command. Signal will remain high until next command is received.
"1" = Mode Code Command was received NCMDSTRB This signal indicates that a completely validated message has been received for standard subaddress data activity. Mode commands with or without data will not generate this signal. The NCMDSTRB signal is 8.5 uS long and is an indication that a DMA burst will initiate at the end of NCMDSTRB to transfer words between the 32 word data memory and the internal main RAM. All subsystem read / writes to the main RAM that have been acknowledged (NACK = "0") before NCMDSTRB has begun must now be completed within 8.5 uS. All subsystem read / write requests to the main RAM initiated after NCMDSTRB has begun will be held off (no acknowledge) until the DMA cycle has been completed. The length of the DMA cycle is dependant on the number of words to DMA into RAM. Access to the 32 word BTL memory is still possible during the DMA cycle by the subsystem. However, transfers between the BTL memory and the main RAM will be locked out. NDBC Active low indicates that the command received by the Remote Terminal was mode code Dynamic Bus Control. Signal will remain low until next command is received.
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NSYNC
Signal to subsystem indicating receipt of a Synchronize mode commands If the mode code has an associated data word, it will be available on T0-T15 at this time. If there is no associated data word, T0-T15 will be zero. Early indication that a Command Word has been received and is being processed. The Command Word received is available on the T0-15 bus for decoding at this time. The user can use this signal for message illegalization and to set the RT Status bits. Access to valid data word in real time before being written to RAM. Data word available on T0-T15 during active low signal. Input to illegalise a command to the Remote Terminal with a clear status response. The signal is sampled after NVCR except non mode code receive commands in which case it is sampled after the last data word has been received. A low on this input will illegalise the message, Command will not be stored in the Command / Status memory and no transfers to / from main RAM will take place. The device will respond with a clear status unless a bit has been specifically set. No data will be transmitted following status.
NVCR
NDATA NILLCMD
BC Discrete Signals
NNEWBUS A Bus Control sequence may not normally be initiated until the current sequence is completed, indicated by signal EOT. However, the Bus Control sequence may be terminated and restarted if NNEWBUS is active low along with write to address 0 00 00 (000h). This feature would only be used in bus switching. EOT Indicates that a valid transfer has been completed on the bus selected. 1 = Valid transfer completed 0 = Not yet Completed Indication that an error has occurred either in the information transferred to the unit from the subsystem or in the transfers on the 1553 data bus. Nature of error is available by reading from register location 0 00 12 (012h). 1 = Error has occurred 0 = No error This signal goes low for 8.5 uS to indicate a valid transfer has been completed on the 1553 data bus and the received Status word is now available on the T0-T15 highway. The Status word is also stored in the Command / Status memory at this time. Once the signal goes high data received by the Bus Controller (RT to BC transfer) will be transferred to the main RAM from the 32 word data buffer memory. Note: Data transferred in RT to RT transfers is not stored in the Bus Controllers main RAM. May be used to illegalise a message just received. Signal can be tied to STATUS for illegalisation due to 1760 checksum failures. A low will prevent any data received being transferred to the main RAM, and the Status word will not be stored in the Command / Status memory.
ERROR
NSTSTRB
NNINHST
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Remote Terminal (RT) Mode
SEQUENCE OF OPERATION
The following section describes the sequence of operation for the various commands that are received by the SmaRT unit in RT Mode.
RECEIVE COMMAND
An incoming command word is verified for all protocol checks (such as parity and bit count). The verified command word is placed on the T0-15 bus and the NVCR signal is strobed. It is at this time that a message can be illegalized. Each successive data word after the command word is placed in an internal buffer FIFO. This is done to double buffer the incoming data for complete message verification. Only after the message is completely validated will the data be transferred to the internal RAM. Otherwise, the contents of the FIFO is automatically flushed. This ensures that only valid data will ever be read by the subsystem. The transfer from the FIFO to the RAM is accomplished by a fast DMA burst. The guarantee of only valid data in RAM greatly simplifies a MIL-STD-1553 RT implementation. Error handling of data is not required by the subsystem. The subsystem is allowed the most flexibility to access the RAM without contending with 1553 bus traffic. In 1553, data words are received at a rate of 20 Sec per word or a maximum time of 640 Sec for a 32 word transfer. Many other systems do not buffer the incoming data at all. That means that the RAM is periodically being updated with data words into the RAM for up to 640 Seconds. If an error occurs, the corrupt data is already in memory and must be sorted out by the subsystem microprocessor. The Smart unit buffers the data so that the RAM is completely available to the subsystem until the DMA transfer to RAM occurs. The possibilities of memory contention is greatly reduced and the contents of RAM is guaranteed to be valid. When the entire set of received data words are transferred to the buffer FIFO, the NCMDSTRB goes low indicating that a completely validated message has been received. The received Command Word again appears on the T0-15 bus at this time. The end of the NCMDSTRB strobe will initiate the DMA cycle to transfer the data words from the buffer FIFO to internal RAM. The NCMDSTRB pulse is 8.5 Sec long and during this time interval, the bus arbitration logic is active. If the subsystem has already begun a read/write operation before NCMDSTRB, the NACK (acknowledge) signal will go low for 500 nSec allowing the completion of the read/write command. The read/write operation must be completed within the remaining 8 Sec. If a read/write operation starts after the NCMDSTRB strobe has begun, the NACK will not occur and thus hold off the subsystem for the duration of the DMA cycle to internal RAM. During NCMDSTRB, the Command Word is loaded into the Command/Status FIFO stack and the NEMPTY line goes high. The user can utilize this signal as an indication that some activity has occurred. The Command/Status FIFO stores up to 32 command words for the subsystem to review. This allows the processor to only response to the 1553 unit when something has occurred. Constant polling of the 1553 unit is not required. To reduce
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processor intervention even further, the Command/Status FIFO will only store commands that have associated data with it.
MESSAGE ILLEGALIZATION
Any message can be illegalized by applying an active low on the NME signal within 600 nSec of the rising edge of NVCR at this time. If NME signal is pulled low, the RT will respond with a Status word having the Message Error bit set.
T0-15
CMD WD
NVCR
NME
500 nSec 600 nSec Max
One way to implement this function is to place a latching PROM to the T0-T10 data bus. The PROM would only have to decode 11 bits (5 bits subaddress, 5 bits word count, 1 bit T/R) and have a one bit output to place a high/low level on the NME input pin. The upper five bits (T11-T15) are just the Remote Terminal address for the unit which is a constant so no decode of these bits are necessary. The latching signal for the PROM would be the NVCR line. The NME pin will be read and acted upon 600 nSec after the rising edge of NVCR. The NME signal would remain latched and stable until the next rising edge of NVCR.
MIL-STD-1760 FEATURES
To enable the 1760 features checksum validation, the NENCHK line is held low. This enables the integrated on-chip hardware checksum features. The hardware automatically checks the incoming message for the correct checksum.
1760 HEADER WORD
The signal NHDR will be an early indicator of the 1760 header word. This headerword will appear on the T0-15 bus when the NHDR signal is low. The NHDR signal will go low on every header word (first data word) even if the 1760 checksum circuitry is enabled or not. NHDR is just an indicator of the first data word on the bus T0-15. T0-15 1760 HDR WD
NHDR 500 nSec
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SIGNALS THAT INDICATE CHECKSUM FAILURE
For 1760 applications, the STATUS line indicates if a message has failed checksum. The STATUS line will toggle up or down for each received data word as it is calculating the checksum and is sampled on the falling edge of NCMDSTRB. The STATUS line can be tied to any of the Status Word Bit inputs to set those bits in the event of a checksum fail. STATUS is an open output line that will set the selected Status Word Bits for the Status Word response in the current message. This is one of the great features for this product. The subsystem does not have to verify the checksum in software to detect the error. The SmaRT unit automatically does this in hardware and the unit is able to flag the error and set the a Status Word Bit on the CURRENT Status Word response . This minimizes processor overhead and reduces response time in notifying the Bus Controller that an error has occurred. For 1760 applications, the NVALCHK signal also indicates a valid checksum for the Receive Command message. NVALCHK is a latched version of the STATUS signal and is updated only on Receive Commands. It is valid on the falling edge of NCMDSTRB of a Receive Command and remains stable until the next Receive Command message. A Transmit Command message will not alter this signal because a Transmit Command does not require an incoming checksum validation.
T0-15 NEMPTY STATUS
CMD WD
VALID
NVALCHK NCMDSTRB 8.5 Sec
Latched Until Next Receive Command
BLOCK TRANSFER LOGIC
The Block Transfer Logic (BTL) may be enabled for both Remote Terminal and Bus Controller. The BTL consists of a 32 word memory buffering the subsystem to the main RAM thus guaranteeing data consistency for both transmit and receive transfers. All reads and writes to the BTL are identical to read / write to the main RAM. The address locations are the same. The only difference is that the BTL circuitry will intercept those read
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/ writes and store them in the buffer instead. The user accesses the same locations as if they would if they were directly accessing the main RAM. The block transfer logic is enabled with signal NENBTL (pin A7) being active low and is not applicable to subaddress 00 and 1F (unless McAir is selected) areas of ram. The block transfer logic may also be configured by writing to certain address locations providing NENBTL is selected, ie. 0 1 00 02 0 1 00 03 0 1 00 04 0 1 00 05 402h 403h 404h 405h Disable Read Disable Read Enable Read Enable Read Disable Write Enable Write Disable Write Enable Write
Reset will enable both Write and Read. Note: All 257X versions with internal RAM that do not have NENBTL as a dsiscrete input have it enabled internally.
READ (RECEIVE)
The Read BTL functions similarly to the Write BTL in that the BTL buffers the read activity. A subsystem read will initially generate a DMA of that entire portion of the subaddress to be stored in the BTL buffer. The subsystem can then read out the data at its leisure while the main RAM is free for future updates. Since the entire portion of the subaddress data was DMA from the RAM, the data read from the BTL buffer is guaranteed contiguous. The user must read data from the device in a specific sequence starting with the first word received in the n-1 location and ending with the last word received in location 00 of the subaddress. The BTL will sense the read from location 00 and reset the sequence ready for a new access. 1. The first word of a received message will be read first, this will initiate a burst DMA transfer of a complete message from main memory to the 32 word BTL buffer memory, during which time the subsystem will be locked out. Data is transferred at the rate of 250 ns per word. 2. The sub system can then read data from the ram at its leisure. The last word to be read will be the last word received in the message and read from location zero. This will reset the block transfer logic. 3. If the 1553 DMA transfer to the main RAM becomes active during the burst transfer, the transfer will complete and then be locked out until the 1553 is complete. However the 32 word BTL buffer memory will be accessible to the subsystem at this time to read out the data. 4. If the 1553 DMA transfer to the main RAM becomes active before the start of the burst transfer, the transfer will belocked out until the 1553 is complete. The sub system will be locked out during this time (main ram being accessed by the 1553 and the 32 word buffer memory is waiting for the receive message). When the 1553 is complete the burst transfer will take place and then unlock the subsystem.
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5. Once the burst transfer has commenced it will complete, thus ensuring data consistency.
DMA TRANSFER TIMES
The DMA cycle transfers words from the FIFO to internal RAM at a rate of one word each 1 Sec. The maximum DMA cycle time could possibly occur for a 32 data word transfer if the RAM is accessed at the beginning of NCMDSTRB Strobe. Maximum subsystem hold-off time would be 8.5 Sec (NCMDSTRB Signal) + 32 Sec (0.5 Sec per word) for a total of 24.5 Sec.
TRANSMIT COMMAND
The incoming command word is verified for all protocol checks (such as parity and bit count). The verified command word is placed on the T0-15 bus and the NVCR signal is strobed. It is at this time that a message can be illegalized.
T0-15
CMD WD
NVCR
NME
500 nSec 600 nSec Max
Any message can be illegalized by applying an active low on the NME signal within 600 nSec of the rising edge of NVCR at this time. The RT will respond with a Status word having the Message Error bit set. See Section 1.2.1.1 for implementing the Message Illegalization. The NCMDSTRB goes low indicating that a completely validated message has been received. The validated Command Word again appears on the T0-15 bus at this time. The end of the NCMDSTRB strobe will initiate the DMA cycle to transfer the data words from internal RAM to the buffer FIFO. Buffering the outgoing message with a FIFO means that the subsystem is allowed the most flexibility to access the RAM without contending with 1553 bus traffic. In 1553, data words are transmitted at a rate of 20 Sec per word or a maximum time of 640 Sec for a 32 word transfer. Many other systems do not buffer the outgoing data at all. That means that the RAM is periodically being accessed for data words from the RAM for up to 640 Seconds. The SmaRT unit buffers the outgoing data so that the RAM is completely available to the subsystem after the DMA transfer from RAM occurs. The possibilities of memory contention is greatly reduced and the contents of the outgoing data will not be affected by subsystem operations. The NCMDSTRB pulse is 8.5 Sec long and during this time interval, the bus arbitration logic is active. If the subsystem has already begun a read/write operation before NCMDSTRB, the NACK (acknowledge) signal will go low for 500 nSec allowing the
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completion of the read/write command. The read/write operation must be completed within the remaining 8 Sec. If a read/write operation starts after the NCMDSTRB strobe has begun, the NACK will not occur and thus hold off the subsystem for the duration of the DMA cycle from internal RAM. During NCMDSTRB, the Command Word is loaded into the Command/Status FIFO stack and the NEMPTY line goes high. The user can utilize this signal as an indication that some activity has occurred. The Command/Status FIFO stores up to 32 command words for the subsystem to review. This allows the processor to only response to the 1553 unit when something has occurred. Constant polling of the 1553 unit is not required. To reduce processor intervention even further, the Command/Status FIFO will only store commands that have associated data with it.
MIL-STD-1760 FEATURES
If the 1760 features are enabled (NENCHK line is held low), the checksum word is automatically generated and transmitted as the last data word. The subsystem processor does not have to calculate or load the checksum word into RAM. The SmaRT unit automatically does this in hardware and transmits the correct checksum data word as the last word out. This reduces subsystem processor overhead significantly.
SIGNALS THAT INDICATE CHECKSUM FAILURE
For 1760 applications, the STATUS line indicates if a message has failed checksum. The STATUS line will stay high for a Transmit Command word because there is no associated data words received for checksum validation. STATUS is sampled on the falling edge of NCMDSTRB. The STATUS line can be tied to any of the Status Word Bit inputs to set those bits in the event of a checksum fail. STATUS is an open output line that will set the selected Status Word Bits for the Status Word response in the current message. This is one of the great features for this product. The subsystem does not have to verify the checksum in software to detect the error. The SmaRT unit automatically does this in hardware and the unit is able to flag the error and set the a Status Word Bit on the CURRENT Status Word response . This minimizes processor overhead and reduces response time in notifying the Bus Controller that an error has occurred. For 1760 applications, the NVALCHK signal does not change from it's previous state since a Transmit Command Word has no incoming data words. NVALCHK is a latched version of the STATUS signal and is updated only on Receive Commands. It is valid on the falling edge of NCMDSTRB of a Receive Command and remains stable until the next Receive Command message. A Transmit Command message will not alter this signal because a Transmit Command does not require an incoming checksum validation.
T0-15
CMD WD
NCMDSTRB
NEMPTY
NVALCHK
***
8.5 Sec
PREVIOUS STATE
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BLOCK TRANSFER LOGIC / DMA TRANSFER TIMES
All reads and writes to the BTL are identical to read / write to the main RAM. The address locations are the same. The only difference is that the BTL circuitry will intercept those read / writes and store them in the buffer instead. The user accesses the same locations as if they would if they were directly accessing the main RAM. The block transfer logic may also be configured by writing to certain address locations providing NENBTL is selected, ie. 0 1 00 02 0 1 00 03 0 1 00 04 0 1 00 05 402h 403h 404h 405h Disable Read Disable Read Enable Read Enable Read Disable Write Enable Write Disable Write Enable Write
Reset will enable both Write and Read.
WRITE
The Write BTL Logic basically stores all writes to a particular subaddress in the buffer until the subsystem has completed the entire subaddress update. When the subsystem has finished, the BTL will generate a burst DMA from the BTL to main RAM in one contiguous transfer. This guarantees that the entire subaddress is updated. Until the DMA transfer the BTL buffer allows the main RAM to be free for updates from the 1553 data bus. The user must write data to the device in a specific sequence starting with the first word for transmission in the n-1 location and ending with the last word for transmission in location 00 of the subaddress. The BTL will sense the write to location 00 and initiate the DMA sequence. 1. Data for one message is written to the 32 word buffer memory at any speed by the subsystem. The first word for transmission is written first to the n-1 location and the last word for transmission is written last to the 00 location of the subaddress. 2. The address of the first word is stored in a register / counter within the "block transfer logic". 3. The last word for transmission is always written to location zero, this will trigger the transfer of data from the 32 word buffer memory to the main memory. Data is transferred at the rate of 250 nS per word. A full 32 word transfer will take approximately 8 uS. 4. If the 1553 is quiet the entire message will immediately be transferred in a single burst to the main memory, the address being generated by the counter within the block transfer logic. During this transfer the subsystem will be locked out via NACK from any new updates. 5. If the 1553 DMA transfer to the main RAM becomes active during the burst transfer, the transfer will complete and then be locked out of any new updates until the 1553 is complete. However the BTL buffer memory will be accessible to the subsystem at this time. 6. If the 1553 DMA transfer to the main RAM becomes active before the start of the burst transfer, the transfer will be locked out (after location zero is written to) until the 1553 is complete. The sub system will be locked out during this time (main ram being accessed
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by the 1553 and the BTL buffer memory is full). If the BTL memory is not fully loaded, the subsystem can continue to load the BTL memory until full (write to 00 indicates a full condition). When the 1553 is complete the burst transfer will take place and then unlock the subsystem. 7. Once the burst transfer has commenced it will complete, thus ensuring data consistency. The DMA cycle begins after the rising edge of NCMDSTRB. All requested data words are placed in an internal buffer FIFO. This is done to double buffer the outgoing data as a contiguous block and free up the internal RAM as quickly as possible. The DMA cycle transfers words from internal RAM at a rate of one word each 1 Sec. The maximum DMA cycle time would occur for a 32 data word transfer or 32 Sec. Maximum subsystem hold-off time would be 8.5Sec + 32 Sec for a total of 40.5 Sec.
CHANGING THE STATUS WORD BITS
There are four Status word bits that can be altered by the subsystem through simple write operations. These four bits and addresses are as follows: SERVREQ 0 0 00 08 008h BUSY 0 0 00 04 004h SSFLAG 0 0 00 02 002h DBCA 0 0 00 01 001h See Memory Map for further details.
DEVICE STATUS
The status of the device may be determined by reading from location 0 00 01, the status bits and BTL status will be available on DATA pins 0-7. DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DBCA SSFLAG SSBUSY SERVREQ BTL WRITE ENABLED BTL READ ENABLED OFF-LINE SELF TEST ENABLED ON-LINE SELF TEST ENABLED
See Memory Map for further details.
BIT REGISTER
With MCAIR (pin F1) disabled, writing data to 0 1 00 13 or 0 1 1F 13 will set the content of the BIT register. The data may also be read from these locations. This register is non-resetable. See Memory Map for further details.
APPLICATION NOTE #108
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Released 9/98
DATA STORAGE AND RETRIEVAL IN RAM
The storage and retrieval of data on RAM is optimized for fast processor accesses. The data (Transmit or Receive) is stored with the first data word (Word #0) in memory location #0n and the last data word (Word #n) in location 00. The processor reads the Command word and extracts the T/R bit, subaddress, and word count bits as a pointer to the proper memory location. The word count field is used as a down counter variable so that a Do Loop routine is executed and then branched out at counter = 00. This may be more efficient in some compilers than an up counter and comparing current loop counter with word count field on every loop. The following section contains sample software pseudo code for data handling. See Memory Map for further details.
SAMPLE SOFTWARE CODE
The following section contains sample pseudo-code for programming and operation the SmaRT unit. The code most resembles Microsoft Quick Basic code (IBM DOS compatible) for simplicity. RETRIEVING OR LOADING DATA TO RAM REM ******************************************************************************************* REM * REM * Routines for operation in Remote Terminal (RT) Mode REM * REM ******************************************************************************************** REM ******************************************************************************************** REM * Variables REM * _______ REM * REM * NCMDEMPTY 0 = EMPTY (NO Command WORDS IN FIFO) REM * 1 = HAVE COMMAND WORDS IN FIFO REM * REM * This signal is derived from NEMPTY REM * on the CT2577. REM * REM * MODE 0 = RT MODE REM * 1 = BC MODE REM * REM * CMDWORD = COMMAND WORD READ FROM FIFO REM * REM * WORDCNT = LOWER 5 BIT OF COMMAND WORD REM * INDICATES HOW MANY DATA WORDS REM * REM * DATA() = DATA ARRAY (32 WORDS MAX) REM * REM * MEMPOINT = LOWER 11 BITS OF THE COMMAND WORD REM * REM * T/R_BIT = BIT #10 OF THE COMMAND WORD REM * REM *
APPLICATION NOTE #108
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REM * REM * REM ******************************************************************************************* REM******************************************************************************************** REM ************ INITIALIZATION ROUTINE *********************************************** REM ******************************************************************************************* INIT: DEFINT A-Z OUT 1, 400(h) "WRITE TO THIS ADDRESS TO SET CT2577 INTO RT MODE INPUT MODE, XX(h) "READ PIN BCNRT FROM THE CT2577 " 0 = RT MODE " 1 = BC MODE DIM DATA(32) "LOCATIONS 1-32 = 32 WORDS REM ****************************************************************************************** REM ****************************************************************************************** REM ************ DETECT COMMAND ROUTINE **************************************** REM ****************************************************************************************** DETECT: IF NCMDEMPTY = 1 THEN CMDWORD = INPUT(OOh) ;READ FROM LOCATION 00 MEMPOINT = CMDWORD & 0000011111111111(b) T/R_BIT = CMDWORD & 0000010000000000(b) WORDCNT = CMDWORD & 0000000000011111(b) MEMPOINT = MEMPOINT - 1 "OFFSET POINTER SO THAT FINAL POSITION "IS AT LOCATION 00. FOR EXAMPLE, A ONE "WORD TRANSFER SHOULD BE LOADED IN "LOCATION 00 OF THAT SUBADDRESS. END IF IF WORDCNT = 00000(b) THEN WORDCNT = 32 "ALL ZEROS IN WORD COUNT FIELD = 32 DATA WORDS END IF IF T/R_BIT = 0000000000000000(b) THEN REDIM DATA() ;CLEARS ARRAY DATA() ; GOT TO ROUTINE TO READ OUT ; THE RECEIVED DATA FROM THE 1553 BUS GOTO RECEIVE END IF IF T/R_BIT = 0000010000000000(b) THEN REDIM DATA() ;CLEARS ARRAY DATA() FOR J = 1 TO 32
APPLICATION NOTE #108
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DATA(J) = XXXX ;LOAD IN DATA FOR TRANSMIT NEXT J GOTO TRANSMIT END IF GOTO END REM *********************************************************************************************** REM *** ROUTINE TO LOAD DATA INTO RAM FROM PROCESSOR ************************* REM *********************************************************************************************** TRANSMIT: FOR I = 1 TO WORDCNT OUTPUT DATA(I), MEMPOINT ; WRITES DATA() INTO LOCATION ; MEMPOINT MEMPOINT = MEMPOINT - 1 NEXT I GOTO END REM ****************************************************************************************************** REM *** ROUTINE TO READ DATA FROM RAM TO PROCESSOR ******************************** REM ****************************************************************************************************** RECEIVE: FOR I = 1 TO WORDCNT DATA(I) = INPUT(MEMPOINT) ; READS LOCATION MEMPOINT INTO ; DATA() ARRAY MEMPOINT = MEMPOINT - 1 NEXT I GOTO END REM ****************************************************************************************************** REM *** ROUTINE TO SCAN FOR MORE MESSAGES **************************************** REM ****************************************************************************************************** END: IF NCMDEMPTY = 1 THEN GOTO DETECT ELSE RETURN ; GO OFF AND DO SOMETHING ELSE ; UNTIL ANOTHER 1553 MESSAGE IS RECEIVED END IF
APPLICATION NOTE #108
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Released 9/98
SELF TEST
The self test feature is an internal and external loop back test for additional verification of functionality. This is in addition to the Remote Terminal Wraparound circuitry. The difference is that this test is manual and under subsystem control. The subsystem microprocessor initiates the self test and the subsequent data word pattern. The subsystem then reads back the wrapped data word and determines if it is correct. The online self test must be done with the 1553 data bus quiet. The self test function is enabled or disabled by writing to certain address locations. Reset will disable self test. 0 1 00 06 0 1 00 07 0 1 00 08 Enable offline self test and set device status bit 6 Enable online self test and set device status bit 7 Disable self test
When self test is enabled the device is set up as both BC and RT. When self test is disabled the device will revert back to its previous state.
BASIC OPERATION
The basic operation is for the BC to transmit the message "receive one data word" and for the RT to receive this message. If the online self test is selected the message will be transmitted onto the 1553 bus via the transceivers and be received by the RT via transceivers. The RT will not respond with Status. If the offline self test is selected the transceivers will be inhibited and the Manchester encoder output is routed to the Manchester decoder input. The status of the device may be obtained by reading from 0 0 00 01. Bit 6 is offline self test enabled. Bit 7 is online self test enabled.
DETAILED OPERATION
1. Enable self test by writing to either 1 00 06 (offline) or 0 1 00 07 (online). 2. Select required 1553 data bus to be tested by writing to 0 0 00 10 or 0 0 00 18.
3. Write the data word contents required for the self test to the appropriate RAM location ie. For broadcast message: 2(bcast) 01-1E(subaddress) 00(1 word) or normal receive message: 0(rec) 01-1E(subaddress) 00(1 word). 4. Initiate BC to RT transfer of one data word by writing to address 0 00 00 with a data word content of 1F or RTaddr 0(rec) 01-1E(subaddress) 01(1 data word). The following automatic sequence is now initiated: a) The Command word (data word written to location 0 0 00 00) is processed by the BC protocol, transferred to the Manchester encoder and transmitted onto the bus (online self test) or to the Manchester decoder (offline self test).
APPLICATION NOTE #108
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b) The self test data word is read from the appropriate RAM location, transferred to the encoder and transmitted contiguously following the command word. c) The Command word is received by the Manchester decoder, if valid and with correct RT address or broadcast is stored in the RT protocol. d) The data word is received by the decoder and if valid is stored in the 32 word data memory. e) The RT protocol will validate the message and if successful will write the Command word to the 32 word Command / Status memory and transfer the data word to the appropriate RAM location. 5. As the data word received is written to the same RAM location that it was originally accessed from, the contents should be altered while the self test is in progress (eg. write 0000). This can be done immediately after the BC to RT transfer was initiated. There is approx 45 us for the self test to complete.
6. To ensure that the RAM contents have been altered it is advisable to read the data back from the RAM. 7. On completion of a successful self test the signal NCMDSTRB will go active low, after which the data can be read from the RAM and compared with the data used in the self test. 8. In addition the Command word used in the self test may be read from 0 00 00. 9. Disable self test by writing to 1 00 08. The device will revert back to its original state (BC or RT).
APPLICATION NOTE #108
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Released 9/98
SUMMARY OF OPERATION
Device can be either RT or BC.
1. ADDR = 1 00 06 (Write) OR ADDR = 1 00 07 (Write) 2. ADDR = 1 00 10 (Write) OR ADDR = 1 00 18 (Write) 3. ADDR = 2 01-1E 00 (Write) DATA = n OR ADDR = 0 01-1E 00 (Write) DATA = n 4. ADDR = 0 00 00 (Write) DATA = 1F 0 01-1E 01 OR ADDR = 0 00 00 (Write) DATA = RTAD 0 01-1E 01 5. ADDR = 2 01-1E 00 (Write) DATA = 0 OR ADDR = 0 01-1E 00 (Write) DATA = 0 6. ADDR = 2 01-1E 00 (Read) DATA = 0 OR ADDR = 0 01-1E 00 (Read) DATA = 0 7. ADDR = 2 01-1E 00 (Read) DATA = n OR ADDR = 0 01-1E 00 (Read) DATA = n 8. ADDR = 0 00 00 (Read) DATA = 1F 0 01-1E 01 OR or ADDR = 0 00 00 (Read) DATA = RTAD 0 01-1E 01 9. ADDR = 1 00 08 (Write) ADDR = 0 00 01 (Read) Select offline self test. Select online self test. Select bus 0. Select bus 1. Write self test data to BCAST location. Write self test data to RECEIVE location. Transmit message (Bcast receive 1 word). Transmit message (Receive 1 word). Write 0 to self test location. Write 0 to self test location. Read 0 from self test location. Read 0 from self test location. Read self test data after NCMDSTRB. Read self test data after NCMDSTRB. Read command from command memory. Read command from command memory. Disable self test. Read device status: Bit 6 = Offline self test. Bit 7 = Online self test
APPLICATION NOTE #108
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Released 9/98
CT2577 /79 RT/BC Device Memory Map Breakdown
The following description is for devices that have internal 3K memory. ALL 'User' Locations are Read/Writable
BCST (Binary) T/R (Binary)
Subaddress (Hex) Word Count (Hex) Composite VME Address 16-bit mode (Hex) Composite VME Address 8-bit mode (Hex) = Lower Byte Upper Byte = Address +1 Composite MULTIbus Address 16-bit mode (Hex)
FUNCTION
0 0 00 00 000 0000 FFF W - Command Word (2nd RT-RT Command) (BC) TRIGGERS BC - BUS 'X' Operation R - Received STATUS (FIFO Stack) (BC) W - Resets ALL Status Bits (RT) R - RT Received COMMAND (RT) 0 0 00 01 001 0002 FFE R/W - 1st RT-RT COMMAND (BC) R/W - Memory Address 002 through 00Fh (BC) W - Sets STATUS Word Flags as Described below (RT) R - ALL Status Bits WRITTEN (RT) via Addresses 001--00F plus BURST Control as Follows: x = Don't Care Y = STATUS Word Bits Selected via WRITEs to 001 through 00Fh B = BURST Control Selected via WRITEs to 402 through 405h xxxx xxxx 00 B B Y Y Y Y DBC SSF BUSY SR BTL WRITE ENABLED (TX) BTL READ ENABLED (RX)
APPLICATION NOTE #108
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RT/BC Device Memory Map Code Breakdown Descriptions
RT STATUS WORD Control Sets
0 0 00 01 0 0 00 02 0 0 00 03 0 0 00 04 0 0 00 05 0 0 00 06 0 0 00 07 0 0 00 08 0 0 00 09 0 0 00 0A 0 0 00 0B 0 0 00 0C 0 0 00 0D 0 0 00 0E 0 0 00 0F 001 002 003 004 005 006 007 008 009 00A 00B 00C 00D 00E 00F 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E FFFE FFFD FFFC FFFB FFFA FFF9 FFF8 FFF7 FFF6 FFF5 FFF4 FFF3 FFF2 FFF1 FFF0 DBC SSFLAG SSFLAG + DBC BUSY BUSY + DBC BUSY + SSFLAG BUSY + SSFLAG + DBC SERVREQ SERVREQ + DBC SERVREQ + SSFLAG SERVREQ + SSFLAG + DBC SERVREQ + BUSY SERVREQ + BUSY + DBC SERVREQ + BUSY + SSFLAG SERVREQ + BUSY + SSFLAG + DBC
BC Control Area
0 0 00 10 010 (18 0020 018 FFEF 0040 BC - SELECT BUS 0 FFE7BC - SELECT BUS 1)
RT/RX BC/TX Mode Area 00 - SA 00 (0) and BC Control
0 0 00 11 0 0 00 12 0 0 00 13 0 0 00 14 0 0 00 15 0 0 00 16 0 0 00 17 0 0 00 18 (10 0 0 00 19 THROUGH 0 0 00 1F 011 012 013 014 015 016 017 018 010 019 01F 0022 0024 0026 0028 002A 002C 002E 0030 0020 0032 003E FFEE FFED FFEC FFEB FFEA FFE9 FFE8 FFE7 FFEF FFE6 FFE0 SYNC WORD ERROR Register User SELECTED TX SHUTDOWN (0000/0001) OVERRIDE SELECTED TX SHUTDOWN (0000/0001) User User BC - SELECT BUS 1 BC - SELECT BUS 0) User User
30 RT Receive / BC Transmit Subaddresses - SA 01-1E (1-30)
0 0 01 00 0 0 01 04 0 0 01 1F 0 0 02 00 0 0 02 1F 0 0 03 00 020 024 03F 040 05F 060 0040 0048 007E 0080 00BE 00C0 FFDF FFDB FFC0 FFBF FFA0 FF9F SA1Last Word (Word 01 if WC =1) Word 01 if WC = 5 Word 01 if WC = 32 SA2 SA3
23
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0 0 03 1F 0 0 04 00 0 0 04 1F 0 0 05 00 0 0 05 1F 0 0 06 00 0 0 06 1F 0 0 07 00 0 0 07 1F 0 0 08 00 0 0 08 1F 0 0 09 00 0 0 09 1F 0 0 0A 00 0 0 0A 1F 0 0 0B 00 0 0 0B 1F 0 0 0C 00 0 0 0C 1F 0 0 0D 00 0 0 0D 1F 0 0 0E 00 0 0 0E 1F 0 0 0F 00 0 0 0F 1F 0 0 10 00 0 0 10 1F 0 0 11 00 0 0 11 00 0 0 12 00 0 0 12 1F 0 0 13 00 0 0 13 1F 0 0 14 00 0 0 14 1F 0 0 15 00 0 0 15 1F 0 0 16 00 0 0 16 1F 0 0 17 00 0 0 17 1F 0 0 18 00 0 0 18 1F 0 0 19 00 0 0 19 1F 0 0 1A 00 0 0 1A 1F 0 0 1B 00 0 0 1B 1F
07F 080 09F 0A0 0BF 0C0 0DF 0E0 0FF 100 11F 120 13F 140 15F 160 17F 180 19F 1A0 1BF 1C0 1DF 1E0 1FF 200 21F 220 23F 240 25F 260 27F 280 29F 2A0 2BF 2C0 2DF 2E0 2FF 300 31F 320 33F 340 35F 360 37F
00FE 0100 013E 0140 017E 0180 01BE 01C0 01FE 0200 023E 0240 027E 0280 02BE 02C0 02FE 0300 033E 0340 037E 0380 03BE 03C0 03FE 0400 043E 0440 047E 0480 04BE 04C0 04FE 0500 053E 0540 057E 0580 05BE 05C0 05FE 0600 063E 0640 067E 0680 06BE 06C0 06FE
FF80 FF7F FF60 FF5F FF40 FF3F FF20 FF1F FF10 FEFF FEE0 FEDF FEC0 FEBF FEA0 FE9F FE80 FE7F FE60 FE5F FE40 FE3F FE20 FE1F FE00 FDFF FDE0 FDDF FDC0 FDBF FDA0 FD9F FD80 FD7F FD60 FD5F FD40 FD3F FD20 FD1F FD00 FCFF FCE0 FCDF FCC0 FCBF FCA0 FC9F FC80
SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27
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0 0 1C 00 0 0 1C 1F 0 0 1D 00 0 0 1D 1F 0 0 1E 00 0 0 1E 1F
380 39F 3A0 3BF 3C0 3DF
0700 073E 0740 077E 0780 07BE
FC7F FC60 FC5F FC40 FC3F FC20
SA28 SA29 SA30
RT/RX BC/TX Mode Area - SA 1F (31)
0 0 1F 00 THROUGH 0 0 1F 10 0 0 1F 11 0 0 1F 12 0 0 1F 13 0 0 1F 14 0 0 1F 15 0 0 1F 16 THROUGH 0 0 1F 1F 3E0 3F0 3F1 3F2 3F3 3F4 3F5 3F6 3FF 07C0 07E0 07E2 07E4 07E6 07E8 07EA 07EC 07FE FC1F FC0F FC0E FC0D FC0C FC0B FC0A FC09 FC00 User User SYNC WORD User User SELECTED TX SHUTDOWN (0000/0001) OVERRIDE SELECTED TX SHUTDOWN (0000/0001) User User
RT/BC Control Area
0 1 00 00 0 1 00 01 400 401 0800 0802 FBFF FBFE SELECT RT SELECT BC
RT/BC Block Transfer Logic (BTL) Control and Self Test Control
0 1 00 02 0 1 00 03 0 1 00 04 0 1 00 05 0 1 00 06 0 1 00 06 0 1 00 06 0 1 00 06 THROUGH 0 1 00 0F 402 403 404 405 406 407 408 409 40F 0804 0806 0808 080A 080C 080E 0810 0812 081E FBFD FBFC FBFB FBFA FBF9 FBF8 FBF7 FBF6 FBF0 RX BTL OFF / TX BTL OFF RX BTL OFF / TX BTL ON RX BTL ON / TX BTL OFF RX BTL ON / TX BTL ON OFF- LINE Self Test ON-LINE Self Test DISABLE Self Test User User
RT/TX BC/RX Mode Area - SA 00 (0)
0 1 00 10 0 1 00 11 0 1 00 12 0 1 00 13 0 1 00 14 THROUGH 0 1 00 1F 410 411 412 413 414 41F 0820 0822 0824 0826 0828 083E FBEF FBDF FBCF FBBF FBAF FBE0 VECTOR WORD User LAST COMMAND BIT WORD User User
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30 RT Transmit / BC Receive Subaddresses - SA 01-1E (1-30)
0 1 01 00 0 1 01 04 0 1 01 1F 0 1 02 00 0 1 02 1F 0 1 03 00 0 1 03 1F 0 1 04 00 0 1 04 1F 0 1 05 00 0 1 05 1F 0 1 06 00 0 1 06 1F 0 1 07 00 0 1 07 1F 0 1 08 00 0 1 08 1F 0 1 09 00 0 1 09 1F 0 1 0A 00 0 1 0A 1F 0 1 0B 00 0 1 0B 1F 0 1 0C 00 0 1 0C 1F 0 1 0D 00 0 1 0D 1F 0 1 0E 00 0 1 0E 1F 0 1 0F 00 0 1 0F 1F 0 1 10 00 0 1 10 1F 0 1 11 00 0 1 11 00 0 1 12 00 0 1 12 1F 0 1 13 00 0 1 13 1F 0 1 14 00 0 1 14 1F 0 1 15 00 0 1 15 1F 0 1 16 00 0 1 16 1F 0 1 17 00 420 424 43F 440 45F 460 47F 480 49F 4A0 4BF 4C0 4DF 4E0 4FF 500 51F 520 53F 540 55F 560 57F 580 59F 5A0 5BF 5C0 5DF 5E0 5FF 600 61F 620 63F 640 65F 660 67F 680 69F 6A0 6BF 6C0 6DF 6E0 0840 0848 087E 0880 08BE 08C0 08FE 0900 093E 0940 097E 0980 09BE 09C0 09FE 0A00 0A3E 0A40 0A7E 0A80 0ABE 0AC0 0AFE 0B00 0B3E 0B40 0B7E 0B80 0BBE 0BC0 0BFE 0C00 0C3E 0C40 0C7E 0C80 0CBE 0CC0 0CFE 0D00 0D3E 0040 0D7E 0D80 0DBE 0DC0 FBDF FBDB FBC0 FBBF FBA0 FB9F FB80 FB7F FB60 FB5F FB40 FB3F FB20 FB1F FB00 FAFF FAE0 FADF FAC0 FABF FAA0 FA9F FA80 FA7F FA60 FA5F FA40 FA3F FA20 FA1F FA00 F9FF F9E0 F9DF F9C0 F9BF F9A0 F99F F980 F97F F960 F95F F940 F93F F920 F91F SA1 Last Word (Word 01 if WC =1) SA1 Word 01 if WC = 5 SA1 Word 01 if WC = 32 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23
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0 1 17 1F 0 1 18 00 0 1 18 1F 0 1 19 00 0 1 19 1F 0 1 1A 00 0 1 1A 1F 0 1 1B 00 0 1 1B 1F 0 1 1C 00 0 1 1C 1F 0 1 1D 00 0 1 1D 1F 0 1 1E 00 0 1 1E 1F
6FF 700 71F 720 73F 740 75F 760 77F 780 79F 7A0 7BF 7C0 7DF
0DFE 0E00 0E3E 0E40 0E7E 0E80 0EBE 0EC0 0EFE 0F00 0F3E 0F40 0F7E 0F80 0FBE
F900 F8FF F8E0 F8DF F8C0 F8BF F8A0 F89F F880 F87F F860 F85F F840 F83F F820
SA24 SA25 SA26 SA27 SA28 SA29 SA30
RT/ TX BC/RX Mode Area - SA 1F (31)
0 1 1F 00 THROUGH 0 1 1F 0F 0 1 1F 10 0 1 1F 11 0 1 1F 12 0 1 1F 13 0 1 1F 14 THROUGH 0 1 1F 1F 7E0 7EF 7F0 7F1 7F2 7F3 7F4 7FF 0FC0 0FDE 0FE0 0FE2 0FE4 0FE6 0FE8 0FFE F81F F810 F80F F80E F80D F80C F80B F800
VECTOR WORD User LAST COMMAND BIT WORD User User
Broadcast RT/RX BC/TX Mode Area - SA 00 (0)
1 0 00 00 THROUGH 1 0 00 10 1 0 00 11 1 0 00 12 1 0 00 13 1 0 00 14 1 0 00 15 1 0 00 16 THROUGH 1 0 00 1F 800 810 811 812 813 814 815 816 81F 1000 1020 1022 1024 1036 1028 102A 102C 103E F7FF F7EF F7EE F7ED F7EC F7EB F7EA F7E9 F7E0 User User SYNC WORD User User SELECTED TX SHUTDOWN (0000/0001) OVERRIDE SELECTED TX SHUTDOWN (0000/0001) User User
30 Broadcast RT Receive / BC Transmit Subaddresses - SA 01-1E (1-30)
1 0 01 00 1 0 01 04 1 0 01 1F 1 0 02 00 1 0 02 1F 820 824 83F 840 85F 1040 1048 107E 1080 10BE F7DF F7DB F7C0 F7BF F7A0 SA1 Last Word (Word 01 if WC =1) SA1 Word 01 if WC = 5 SA1 Word 01 if WC = 32 SA2
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1 0 03 00 1 0 03 1F 1 0 04 00 1 0 04 1F 1 0 05 00 1 0 05 1F 1 0 06 00 1 0 06 1F 1 0 07 00 1 0 07 1F 1 0 08 00 1 0 08 1F 1 0 09 00 1 0 09 1F 1 0 0A 00 1 0 0A 1F 1 0 0B 00 1 0 0B 1F 1 0 0C 00 1 0 0C 1F 1 0 0D 00 1 0 0D 1F 1 0 0E 00 1 0 0E 1F 1 0 0F 00 1 0 0F 1F 1 0 10 00 1 0 10 1F 1 0 11 00 1 0 11 00 1 0 12 00 1 0 12 1F 1 0 13 00 1 0 13 1F 1 0 14 00 1 0 14 1F 1 0 15 00 1 0 15 1F 1 0 16 00 1 0 16 1F 1 0 17 00 1 0 17 1F 1 0 18 00 1 0 18 1F 1 0 19 00 1 0 19 1F 1 0 1A 00 1 0 1A 1F 1 0 1B 00
860 87F 880 89F 8A0 8BF 8C0 8DF 8E0 8FF 900 91F 920 93F 940 95F 960 97F 980 99F 9A0 9BF 9C0 9DF 9E0 9FF A00 A1F A20 A3F A40 A5F A60 A7F A80 A9F AA0 ABF AC0 ADF AE0 AFF B00 B1F B20 B3F B40 B5F B60
10C0 10FE 1100 113E 1140 117E 1180 11BE 11C0 11FE 1200 123E 1240 127E 1280 12BE 12C0 12FE 1300 133E 1340 137E 1380 13BE 13C0 133E 1400 143E 1440 147E 1480 14BE 14C0 14FE 1500 153E 1540 157E 1580 15BE 15C0 15FE 1600 163E 1640 167E 1680 16BE 16C0
F79F F780 F77F F760 F75F F740 F73F F720 F71F F700 F6FF F6E0 F6DF F6C0 F6BF F6A0 F69F F680 F67F F660 F65F F640 F63F F620 F61F F600 F5FF F5E0 F5DF F5C0 F5BF F5A0 F59F F580 F57F F560 F55F F540 F53F F520 F51F F500 F4FF F4E0 F4DF F4C0 F4BF F4A0 F49F
SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27
28
APPLICATION NOTE #108
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1 0 1B 1F 1 0 1C 00 1 0 1C 1F 1 0 1D 00 1 0 1D 1F 1 0 1E 00 1 0 1E 1F
B7F B80 B9F BA0 BBF BC0 BDF
16FE 1700 173E 1740 177E 1780 17BE
F480 F47F F460 F45F F440 F43F F420
SA28 SA29 SA30
Broadcast RT/RX BC/TX Mode Area 1F - SA 1F (31)
1 0 1F 00 THROUGH 1 0 1F 10 1 0 1F 11 1 0 1F 12 1 0 1F 13 1 0 1F 14 1 0 1F 15 1 0 1F 16 THROUGH 1 0 1F 1F BE0 BF0 BF1 BF2 BF3 BF4 BF5 BF6 BFF 17C0 17E0 17E2 17E4 17E6 17E8 17EA 17EC 17FE F41F F40F F40E F40D F40C F40B F40A F409 F400 User User SYNC WORD User User SELECTED TX SHUTDOWN (0000/0001) OVERRIDE SELECTED TX SHUTDOWN (0000/0001) User User
APPLICATION NOTE #108
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CT2577 / 79 Part Ordering Information
APPLICATION NOTE #108
30
Released 9/98
CT2577 - Mil-Std 1553 / 1760 Bus Controller/Remote Terminal
CT2577- XX- YY- ZZ
P 1 1 9 = 119 Pin PGA F 8 4 = 84 Pin Quad Flatpack QM XT IN CG XX = Full Mil 883C Screened Part (-550C to +1250C) = Extended Temperature Range (-550C to +1250C) = Industrial Temperature Range (-400C to +850C) = Commercial Grade (00C to +700C) = Function Selection
0 = Memory Enabled (T0-T15 Bus) 1 = Memory Enabled (T0-T10 Bus) 0 = No Stores Pinout 1 = Stores Pinout
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CT2578 - Mil-Std 1553 / 1760 Bus Remote Terminal Only
CT2578- XX- YY- ZZ
P 1 1 9 = 119 Pin PGA F 8 4 = 84 Pin Quad Flatpack QM XT IN CG XX = Full Mil 883C Screened Part (-550C to +1250C) = Extended Temperature Range (-550C to +1250C) = Industrial Temperature Range (-400C to +850C) = Commercial Grade (00C to +700C) = Function Selection
0 = Memory Enabled (T0-T15 Bus) 1 = Memory Enabled (T0-T10 Bus) 2 = No Memory Enabled (DMA) 0 = No Stores Pinout 1 = Stores Pinout
APPLICATION NOTE #108
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CT2579 - McAir Bus Remote Controller/Remote Terminal
CT2579- XX- YY- ZZ
P 1 1 9 = 119 Pin PGA F 8 4 = 84 Pin Quad Flatpack QM XT IN CG XX = Full Mil 883C Screened Part (-550C to +1250C) = Extended Temperature Range (-550C to +1250C) = Industrial Temperature Range (-400C to +850C) = Commercial Grade (00C to +700C) = Function Selection
0 = Memory Enabled (T0-T15 Bus) 1 = Memory Enabled (T0-T10 Bus) 0 = No Stores Pinout 1 = Stores Pinout
APPLICATION NOTE #108
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CT2580 - McAir Bus Remote Terminal Only
CT2580- XX- YY- ZZ
P 1 1 9 = 119 Pin PGA F 8 4 = 84 Pin Quad Flatpack QM XT IN CG XX = Full Mil 883C Screened Part (-550C to +1250C) = Extended Temperature Range (-550C to +1250C) = Industrial Temperature Range (-400C to +850C) = Commercial Grade (00C to +700C) = Function Selection
0 = Memory Enabled (T0-T15 Bus) 1 = Memory Enabled (T0-T10 Bus) 0 = No Stores Pinout 1 = Stores Pinout
APPLICATION NOTE #108
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Released 9/98
CT2577 / 79 Pinouts
APPLICATION NOTE #108
35
Released 9/98
CT2577-01-xx-F84 Pinouts - 84 Pin Quad Flatpack
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Description ADIN 11 ADIN 10 ADIN 09 BCNRT NSYNC ADIN 08 Not Connected Not Connected ADIN 07 ADIN 06 MCDET NVCR BCST NTF ADIN 05 ADIN 04 NME ADDR E NDBC EOT ADDR D ADDR C ADDR B NWR ADDR A NRD NACK ADDR P DATA (Bus 0 ) NDATA (Bus 0 ) NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ LA ADIN 03 ADIN 02 ADIN 01 NRES/NRCL ADIN 00 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description NCMDSTRB NEMPTY DATA 00 DATA 01 NSSFLAG UB NBIT16 Not Connected DATA 02 Not Connected DATA 03 DATA 04 DATA 05 WRAPEN DATA 06 T 00 DATA 07 DATA 08 T 01 T 02 DATA 09 DATA 10 DATA 11 T 03 T 04 T 05 DATA 12 T 06 DATA 13 DATA 14 T 07 DATA (Bus 1) NDATA (Bus 1 ) NFULL DATA 15 VDD2 VSS2 NILLCMD T 08 T 09 T 10 VME(/MULTI)
APPLICATION NOTE #108
36
Released 9/98
CT2577-11-xx-F84 Pinouts - 84 Pin Quad Flatpack
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Description ADIN 11 ADIN 10 ADIN 09 BCNRT NSYNC ADIN 08 NVALCHK (1760) STATUS (1760) ADIN 07 ADIN 06 NENCHK (1760) NVCR BCST NTF ADIN 05 ADIN 04 NME ADDR E NDBC EOT ADDR D ADDR C ADDR B NWR ADDR A NRD NACK ADDR P DATA (Bus 0) NDATA (Bus 0) NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ LA ADIN 03 ADIN 02 ADIN 01 NRES/NRCL ADIN 00 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description NCMDSTRB NEMPTY DATA 00 DATA 01 NSSFLAG UB NBIT16 NHDR (1760) DATA 02 STREL (1760) DATA 03 DATA 04 DATA 05 WRAPEN DATA 06 T 00 DATA 07 DATA 08 T 01 T 02 DATA 09 DATA 10 DATA 11 T 03 T 04 T 05 DATA 12 T 06 DATA 13 DATA 14 T 07 DATA (Bus 1) NDATA (Bus 1) NFULL DATA 15 VDD2 VSS2 NILLCMD T 08 T 09 T 10 VME(/MULTI)
APPLICATION NOTE #108
37
Released 9/98
CT2579-01-xx-F84 Pinouts - 84 Pin Quad Flatpack
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Description ADIN 11 ADIN 10 ADIN 09 BCNRT NSYNC ADIN 08 Not Connected Not Connected ADIN 07 ADIN 06 MCDET NVCR BCST NTF ADIN 05 ADIN 04 NME ADDR E NDBC EOT ADDR D ADDR C ADDR B NWR ADDR A NRD NACK ADDR P DATA (Bus 0) NDATA (Bus 0) NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ LA ADIN 03 ADIN 02 ADIN 01 NRES/NRCL ADIN 00 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description NCMDSTRB NEMPTY DATA 00 DATA 01 NSSFLAG UB NBIT16 Not Connected DATA 02 Not Connected DATA 03 DATA 04 DATA 05 WRAPEN DATA 06 T 00 DATA 07 DATA 08 T 01 T 02 DATA 09 DATA 10 DATA 11 T 03 T 04 T 05 DATA 12 T 06 DATA 13 DATA 14 T 07 DATA (Bus 1) NDATA (Bus 1) NFULL DATA 15 VDD2 VSS2 NILLCMD T 08 T 09 T 10 VME(/MULTI)
APPLICATION NOTE #108
38
Released 9/98
CT2579-11-xx-F84 Pinouts - 84 Pin Quad Flatpack
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Description ADIN 11 ADIN 10 ADIN 09 BCNRT NSYNC ADIN 08 NVALCHK (1760) STATUS (1760) ADIN 07 ADIN 06 NENCHK (1760) NVCR BCST NTF ADIN ADIN NME ADDR E NDBC EOT ADDR D ADDR C ADDR B NWR ADDR A NRD NACK ADDR P DATA (Bus 0) NDATA (Bus 0) NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ LA ADIN ADIN ADIN NRES/NRCL ADIN 00 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description NCMDSTRB NEMPTY DATA 00 DATA 01 NSSFLAG UB NBIT16 NHDR (1760) DATA 02 STREL (1760) DATA 03 DATA 04 DATA 05 WRAPEN DATA 06 T 00 DATA 07 DATA 08 T 01 T 02 DATA 09 DATA 10 DATA 11 T 03 T 04 T 05 DATA 12 T 06 DATA 13 DATA 14 T 07 DATA (Bus 1) NDATA (Bus 1) NFULL DATA 15 VDD2 VSS2 NILLCMD T 08 T 09 T 10 VME(/MULTI)
APPLICATION NOTE #108
39
Released 9/98
CT2577-10-xx-P119 Pinouts - 119 Pin Grid Array
Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 Description VME T 11 T9 T8 N/C N/C NENBTL DATA 15 DATA 1(BUS) T7 T6 DATA 12 T3 ADIN 11 T 12 N/C N/C N/C N/C VSS NFULL N/C DATA 13 T4 DATA 10 DATA 9 T 14 INITWD T 10 N/C NILLCMD VDD NDATA 1(BUS) DATA 14 T5 DATA 11 T1 DATA 8 ADIN 9 ADIN 10 Pin # D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 Description T 13 T2 DATA 7 DATA 6 NSYNC BCNRT T 15 T0 WRAPEN DATA 5 MCAIR N/C ADIN 8 DATA 4 NSR DATA 3 NVALCHK ADIN 7 STATUS DATA 2 STREL NHDR ADIN 6 NENCHK MCDET NBUSY N/C NBIT16 WATCHDOG NVCR NTF DATA 0 NSSFLAG UB BCST ADIN 5 ADDR E NNEWBUS SELEN 1 DATA 1 Pin # L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Description ADIN 4 NME EOT ADDR B NACK NDATA 0 (BUS) VDD NINHST ADIN 3 ADIN 0 NCMDSTRB NDBCA NTXINH 1 SELEN 0 NDBC ADDR C NRD N/C NSTSTRB VSS INHMC LA ADIN 2 NRES N/C NTXINH 0 ADDR D NWR ADDR A ADDR P DATA 0(BUS) NCARDEN ERROR N/C C16MHZ NDATA ADIN 1 N/C NEMPTY
APPLICATION NOTE #108
40
Released 9/98
CT2579-10-xx-P119 Pinouts - 119 Pin Grid Array
Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 Description VME T 11 T9 T8 N/C N/C NENBTL DATA 15 DATA 1(BUS) T7 T6 DATA 12 T3 ADIN 11 T 12 N/C N/C N/C N/C VSS NFULL N/C DATA 13 T4 DATA 10 DATA 9 T 14 INITWD T 10 N/C NILLCMD VDD NDATA 1(BUS) DATA 14 T5 DATA 11 T1 DATA 8 ADIN 9 ADIN 10 Pin # D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 Description T 13 T2 DATA 7 DATA 6 NSYNC BCNRT T 15 T0 WRAPEN DATA 5 MCAIR N/C ADIN 8 DATA 4 NSR DATA 3 NVALCHK ADIN 7 STATUS DATA 2 STREL NHDR ADIN 6 NENCHK MCDET NBUSY N/C NBIT16 WATCHDOG NVCR NTF DATA 0 NSSFLAG UB BCST ADIN 5 ADDR E NNEWBUS SELEN 1 DATA 1 Pin # L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Description ADIN 4 NME EOT ADDR B NACK NDATA 0 (BUS) VDD NINHST ADIN 3 ADIN 0 NCMDSTRB NDBCA NTXINH 1 SELEN 0 NDBC ADDR C NRD N/C NSTSTRB VSS INHMC LA ADIN 2 NRES N/C NTXINH 0 ADDR D NWR ADDR A ADDR P DATA 0(BUS) NCARDEN ERROR N/C C16MHZ NDATA ADIN 1 N/C NEMPTY
APPLICATION NOTE #108
41
Released 9/98

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